OCR A Level Computer Science Unit 1.1

Course Overview

This topic covers everything you need to know about processor architecture for your OCR A-Level Computer Science exam. You'll explore the CPU's internal components, learn how instructions are processed, and understand what makes some processors faster than others.

The content includes five key areas: CPU components, the fetch-decode-execute cycle, performance factors, pipelining techniques, and different architectural approaches. These concepts build on each other, so mastering the basics will make the advanced topics much easier to grasp.

Quick Tip: Focus on understanding how each component works together rather than memorising isolated facts—this will help you tackle those tricky exam questions with confidence.

Components of the CPU

Think of the CPU as a highly organised factory that processes every piece of data in your computer. It's made up of several key components that work together seamlessly.

The Arithmetic and Logic Unit (ALU) handles all calculations and logical operations like AND, OR, and NOT. Meanwhile, the Control Unit (CU) acts like a supervisor, decoding instructions and controlling data flow throughout the processor.

Registers are ultra-fast temporary storage locations inside the CPU, each with a specific job. The Program Counter (PC) keeps track of the next instruction's address, whilst the Accumulator (ACC) temporarily holds values during calculations.

Other crucial registers include the Memory Address Register (MAR) for storing addresses, the Memory Data Register (MDR) for holding data being transferred, and the Current Instruction Register (CIR) where instructions are prepared for decoding.

Remember: Registers are much faster than RAM because they're built directly into the CPU—that's why they're used for critical, frequently-accessed data.

CPU Architecture Diagram

The CPU connects to main memory through a sophisticated system of buses—think of them as highways for data. This diagram shows how all components work together in practice.

The ALU contains several sub-components: arithmetic circuits for maths operations, logic circuits for comparisons, additional registers for temporary storage, and status flags that signal important conditions like overflow errors.

Buses are the communication channels that make everything possible. The data bus carries actual information, the address bus specifies where data should go, and the control bus manages whether operations are reading or writing data.

This interconnected system ensures that data flows efficiently between the CPU and memory, with each component playing its specific role in the processing pipeline.

Exam Focus: You'll often get questions asking you to trace data flow through these components—practice following the paths data takes through different registers and buses.

Component Functions

Each CPU component has a specific role that's essential for processing instructions effectively. The Control Unit is where the magic of instruction decoding happens—it interprets what each instruction means and coordinates the entire operation.

Registers each serve unique purposes. The Program Counter always points to the next instruction, automatically incrementing as the processor works through your program. The Accumulator is your temporary workspace for calculations and data manipulation.

The Memory Address Register and Memory Data Register work as a team for all memory operations. MAR holds the address you want to access, whilst MDR contains the actual data being transferred to or from that location.

When instructions arrive from memory, they're temporarily stored in the Current Instruction Register before being split into their opcode (what to do) and operand (what to do it with) components.

Key Insight: Understanding these register functions is crucial for tracing through assembly language programs—each instruction type uses specific registers in predictable ways.

Bus Systems

Buses are the communication superhighways that connect your CPU to the rest of the computer system. Each of the three main buses has a specific job that's essential for proper operation.

The data bus is bidirectional, meaning information can flow both ways—from CPU to memory when storing data, and from memory to CPU when loading it. This flexibility is crucial for efficient data processing.

The address bus carries location information, telling the system exactly where to find or store data in memory. Meanwhile, the control bus acts like a traffic controller, sending signals that determine whether the other buses are reading or writing.

Additional buses within the CPU itself transport data between different internal components, ensuring smooth coordination between registers, the ALU, and the control unit.

Quick Check: Remember that buses work together—you can't just send data without specifying where it goes (address) and what type of operation you're performing (control).

Fetch-Decode-Execute Cycle

The fetch-decode-execute cycle is the fundamental process that makes your computer work—it's happening billions of times per second right now as you read this! This three-stage cycle repeats continuously while your computer runs.

Fetching involves getting the next instruction from memory. The Program Counter provides the address, which gets copied to the MAR. The instruction then travels from memory through the data bus to the MDR, whilst the PC increments to point to the next instruction.

Decoding happens when the instruction moves from the MDR to the CIR, where it's split into opcode and operand parts. The Control Unit then interprets what action needs to be performed.

Execution varies depending on the instruction type—input operations use the ACC, memory operations involve the MAR and MDR, and calculations happen in the ALU. Each instruction type follows predictable register usage patterns.

Exam Success: Practice tracing through this cycle with specific instructions—understanding which registers are used when will help you tackle assembly language questions confidently.

Assembly Language Example

Working through assembly language examples helps you understand how the fetch-decode-execute cycle operates in practice. Each instruction type uses specific registers in predictable ways.

When executing STA count (store accumulator), the process involves three key registers. The ACC contains the value to be stored, the MAR holds the memory address (like location 16), and the MDR temporarily holds the data before it's written to memory.

LDA operations work in reverse—loading data from memory into the accumulator. ADD and SUB instructions use the ALU for calculations, whilst branching instructions like BRA and BRZ involve comparisons to determine program flow.

Understanding these patterns makes assembly language much more manageable. Each instruction follows logical steps that you can predict once you know the basic principles.

Top Tip: When answering register questions, always include specific values from the question—examiners want to see that you understand both which registers are used AND what they contain.

Worked Example Analysis

This STA count example demonstrates exactly how to approach assembly language questions in your exam. The key is being specific about register contents, not just identifying which registers are involved.

With the accumulator holding value 9 and count referring to memory location 16, you can trace the exact data flow. The value 9 moves from ACC to MDR, whilst the address 16 goes to MAR to specify the storage location.

Memory addressing can be tricky—you might need to count instruction lines to work out memory locations if they're not given. Remember that programs start at memory location 0, so count carefully from the beginning.

The examiner wants to see that you understand both the process and the specific values involved. Generic answers about register usage won't earn full marks without the concrete details from the question.

Exam Strategy: Always write down line numbers when working with assembly code—this helps you track memory locations and avoid counting errors that could cost you marks.

CPU Performance Factors

CPU performance depends on three main factors that work together to determine how quickly your processor can handle tasks. Understanding these helps explain why some computers are faster than others.

Clock speed measures how many cycles your CPU completes per second. A typical 2.3 GHz processor performs over 2 billion cycles per second! Higher clock speeds generally mean faster performance, though some complex instructions require multiple cycles.

Multiple cores allow parallel processing—different cores can work on separate tasks simultaneously. However, a dual-core processor isn't exactly twice as fast as single-core because there's overhead in coordinating between cores, and some tasks can't be split up.

The effectiveness of multiple cores depends heavily on the type of work being done. Video editing and gaming benefit greatly from multiple cores, whilst simple tasks like word processing might not see much improvement.

Real-World Connection: This is why your phone might have 8 cores but still sometimes feels slow—it's not just about the number of cores, but how well the software can use them.

Cache Memory System

Cache memory is like having a super-fast notepad right next to your workspace—it stores frequently used data and instructions much closer to the CPU than regular RAM, dramatically speeding up access times.

The cache uses a three-level hierarchy designed for optimal performance. Level 1 is the smallest and fastest, with dedicated cache for each core. Level 2 is larger but slightly slower, typically shared between cores.

Level 3 cache is the largest and slowest of the three levels, usually located on the motherboard rather than within the CPU itself. This hierarchical system balances speed with storage capacity effectively.

When you revisit websites or run familiar programs, they load faster because key data is stored in cache. The cache automatically updates when content changes, ensuring you always get current information whilst maintaining speed benefits.

Memory Tip: Think of cache levels like your desk drawer (L1), filing cabinet (L2), and storage room (L3)—closer storage is faster but has less space.