The Fetch-decode-execute cycle is a fundamental concept in computer architecture that explains how a computer's CPU processes and executes instructions.
The cycle consists of three main stages that work together to run programs:
Fetch: The CPU retrieves the next instruction from memory using the program counter (PC). The instruction is loaded into the instruction register (IR) while the PC increments to point to the next instruction.
Decode: The control unit decodes the instruction in the IR to determine what operation needs to be performed. This involves breaking down the instruction into its component parts like the operation code (opcode) and operands.
Execute: The decoded instruction is carried out by the arithmetic logic unit (ALU) or other CPU components. This could involve calculations, moving data between registers, or accessing memory. The results are stored in appropriate registers.
For students studying GCSE Computer Science OCR or preparing with OCR GCSE Computer Science revision resources, understanding this cycle is crucial. The cycle repeats continuously while a program runs, with each instruction going through all three stages. Modern CPUs use techniques like pipelining to optimize this process, allowing multiple instructions to be processed simultaneously at different stages. The cycle is essential for explaining how computers execute software instructions and forms the basis for more advanced concepts in computer architecture.
This fundamental process is frequently tested in OCR GCSE Computer Science past papers and features prominently in GCSE Computer Science revision notes PDF materials. Students should be able to explain each stage in detail, understand how the cycle relates to program execution, and recognize how different components of the CPU (like the ALU, control unit, and registers) work together during each stage. The cycle demonstrates the sequential nature of program execution and helps explain why computers can only process one instruction at a time in its most basic form, though modern architectures have evolved to handle multiple instructions simultaneously through various optimization techniques.